Invention Grant
- Patent Title: Method of compensating charge loss and source line bias in programing of non-volatile memory device
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Application No.: US16402237Application Date: 2019-05-03
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Publication No.: US10783959B2Publication Date: 2020-09-22
- Inventor: Chun-Yi Tu , Ming-Chang Tsai , Jui-Lung Weng
- Applicant: Powerchip Technology Corporation
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee: Powerchip Semiconductor Manufacturing Corporation
- Current Assignee Address: TW Hsinchu
- Agent Winston Hsu
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@67e7dac7
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C29/52 ; G11C16/10 ; G11C5/14 ; G11C16/34 ; G11C16/26 ; G11C16/16
Abstract:
A method of compensating charge loss and source line bias in programing of non-volatile memory device including the steps of reading a previous program page with a low reference voltage to make an original previous program pattern, merging the original previous program pattern and a current program pattern to make a merged program pattern, reading the previous program page with a high reference voltage to make a verified previous program pattern, and merging the verified previous program pattern and the merged program pattern to make a compensated current program pattern.
Public/Granted literature
- US20200219561A1 METHOD OF COMPENSATING CHARGE LOSS AND SOURCE LINE BIAS IN PROGRAMING OF NON-VOLATILE MEMORY DEVICE Public/Granted day:2020-07-09
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