An in-memory computation device is described that comprises a memory with a plurality of blocks B(n) of cells, where n ranges from 0 to N−1. A page output circuit PO(n) and page input circuit PI(n) are operatively coupled to block B(n) in the plurality of sets. A data bus system for providing an external source of input data and a destination for output data is provided. Data circuits are configurable connect page input circuit PI(n) to one or more of page output circuit PO(n), page output circuit PO(n−1), and the data bus system to source the page input data in a sensing cycle. This configuration can be done between each sensing cycle, or in longer intervals, in order to support a variety of neural network configurations and operations.