A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.