Invention Grant
- Patent Title: Methods for parity error synchronization and memory devices and systems employing the same
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Application No.: US15975697Application Date: 2018-05-09
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Publication No.: US10783980B2Publication Date: 2020-09-22
- Inventor: William C. Waldrop , Vijayakrishna J. Vankayala
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G06F11/10 ; G06F11/16 ; G11C7/22 ; G11C11/4076 ; G11C11/408 ; G11C11/16 ; G11C7/10 ; G11C29/02 ; G06F13/16 ; G11C29/52
Abstract:
Systems and methods providing for a parity error synchronization based on a programmed parity latency value by delaying an activation of a command disable signal to disable internal commands such that the command disable signal activates just prior to the parity error command.
Information query
