Invention Grant
- Patent Title: Semiconductor package and method
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Application No.: US15907869Application Date: 2018-02-28
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Publication No.: US10784203B2Publication Date: 2020-09-22
- Inventor: Tzu-Sung Huang , Hsiu-Jen Lin , Hao-Yi Tsai , Ming Hung Tseng , Tsung-Hsien Chiang , Tin-Hao Kuo , Yen-Liang Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/768 ; H01L23/498 ; H01L23/00

Abstract:
In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
Public/Granted literature
- US20190148301A1 Semiconductor Package and Method Public/Granted day:2019-05-16
Information query
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