Invention Grant
- Patent Title: Process control for package formation
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Application No.: US16121861Application Date: 2018-09-05
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Publication No.: US10784247B2Publication Date: 2020-09-22
- Inventor: Ming-Fa Chen , Hsien-Wei Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L23/00 ; H01L23/538 ; H01L23/48 ; H01L21/768 ; H01L23/31 ; H01L25/03 ; H01L21/56 ; H01L25/10 ; H01L25/18 ; H01L25/065

Abstract:
A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.
Public/Granted literature
- US20190148351A1 Process Control for Package Formation Public/Granted day:2019-05-16
Information query
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