Invention Grant
- Patent Title: Integrated circuit and layout design method
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Application No.: US16282419Application Date: 2019-02-22
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Publication No.: US10784249B2Publication Date: 2020-09-22
- Inventor: Hirokazu Okano
- Applicant: Kabushiki Kaisha Toshiba , Toshiba Electronic Devices & Storage Corporation
- Applicant Address: JP Tokyo JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee: Kabushiki Kaisha Toshiba,Toshiba Electronic Devices & Storage Corporation
- Current Assignee Address: JP Tokyo JP Tokyo
- Agency: White & Case LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@6ff32ff6
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/02 ; G06F30/394

Abstract:
According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.
Public/Granted literature
- US20200091132A1 INTEGRATED CIRCUIT AND LAYOUT DESIGN METHOD Public/Granted day:2020-03-19
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