- Patent Title: Field effect transistor devices with buried well protection regions
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Application No.: US16173556Application Date: 2018-10-29
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Publication No.: US10784338B2Publication Date: 2020-09-22
- Inventor: Lin Cheng , Anant Agarwal , Vipindas Pala , John Palmour
- Applicant: Cree, Inc.
- Applicant Address: US NC Durham
- Assignee: Cree, Inc.
- Current Assignee: Cree, Inc.
- Current Assignee Address: US NC Durham
- Agency: Myers Bigel, P.A.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L29/66 ; H01L29/739 ; H01L29/16 ; H01L29/10 ; H01L21/04

Abstract:
A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.
Public/Granted literature
- US20190067414A1 FIELD EFFECT TRANSISTOR DEVICES WITH BURIED WELL PROTECTION REGIONS Public/Granted day:2019-02-28
Information query
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