Invention Grant
- Patent Title: Castellated superjunction transistors
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Application No.: US16252952Application Date: 2019-01-21
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Publication No.: US10784341B2Publication Date: 2020-09-22
- Inventor: Josephine Bea Chang , Eric J. Stewart , Ken Alfred Nagamatsu , Robert S. Howell , Shalini Gupta
- Applicant: Josephine Bea Chang , Eric J. Stewart , Ken Alfred Nagamatsu , Robert S. Howell , Shalini Gupta
- Applicant Address: US VA Falls Church
- Assignee: NORTHROP GRUMNIAN SYSTEMS CORPORATION
- Current Assignee: NORTHROP GRUMNIAN SYSTEMS CORPORATION
- Current Assignee Address: US VA Falls Church
- Agency: Tarolli, Sundheim, Covell & Tummino LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/08 ; H01L23/29 ; H01L23/31 ; H01L29/15 ; H01L29/423 ; H01L21/02 ; H01L21/306 ; H01L29/778 ; H01L29/66
Abstract:
A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
Public/Granted literature
- US20200235202A1 CASTELLATED SUPERJUNCTION TRANSISTORS Public/Granted day:2020-07-23
Information query
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