Invention Grant
- Patent Title: Digital to analog converter tolerant to element mismatch
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Application No.: US16724195Application Date: 2019-12-21
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Publication No.: US10784878B1Publication Date: 2020-09-22
- Inventor: Amrith Sukumaran , Gireesh Rajendran , Ashish Lachhwani
- Applicant: Steradian Semiconductors Private Limited
- Main IPC: H03M1/06
- IPC: H03M1/06 ; H03M1/14 ; H03M1/78 ; H03H11/30

Abstract:
According to an aspect, a tri-level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with a first error as an output for a first digital value, a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state.
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