A computer executable tool analyzes a gate-level netlist and uses an analysis result for accelerating a timing-accurate gate-level logic simulation via a parallel processing. The analysis identifies the following elements in the gate-level netlist: (1) netlist wires at partition boundaries for a value propagation; (2) netlist wires whose activities should be suppressed for a better performance; and (3) upstream FFs for partition boundaries to reduce a synchronization overhead. This information is then used to improve a parallel simulation performance.