A memory controller controlling a semiconductor memory device, the memory controller may comprises a host interface configured to receive a write request, from a host, to store data in the semiconductor memory device, a processor configured to generate a program command according to a type of the write request, a memory interface configured to provide the program command to the semiconductor memory device, wherein the type of the write request includes a first type write request and a second type write request, and wherein the first type write request requires faster write completion response than the second type write request.