Invention Grant
- Patent Title: Wear-leveling scheme for memory subsystems
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Application No.: US16127025Application Date: 2018-09-10
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Publication No.: US10795810B2Publication Date: 2020-10-06
- Inventor: Samuel E. Bradshaw , Justin Eno
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/1009 ; G06F3/06

Abstract:
A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.
Public/Granted literature
- US20200081829A1 Wear-Leveling Scheme for Memory Subsystems Public/Granted day:2020-03-12
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