Invention Grant
- Patent Title: Multi-processor system with configurable cache sub-domains and cross-die memory coherency
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Application No.: US16453670Application Date: 2019-06-26
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Publication No.: US10795819B1Publication Date: 2020-10-06
- Inventor: Robert Pawlowski , Bharadwaj Krishnamurthy , Vincent Cave , Jason M. Howard , Ankit More , Joshua B. Fryman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson de vos Webster & Elliott LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0817 ; G06F12/0811 ; G06F9/38 ; G06F9/30 ; G06F12/0891

Abstract:
Disclosed embodiments relate to a system with configurable cache sub-domains and cross-die memory coherency. In one example, a system includes R racks, each rack housing N nodes, each node incorporating D dies, each die containing C cores and a die shadow tag, each core including P pipelines and a core shadow tag, each pipelines associated with a data cache and data cache tags and being either non-coherent or coherent and one of X coherency domains, wherein each pipeline, when needing to read a cache line, issues a read request to its associated data cache, then, if need be, issues a read request to its associated core-level cache, then, if need be, issues a read request to its associated die-level cache, then, if need be, issues a no-cache remote read request to a target die being mapped to hold the cache line.
Information query