Invention Grant
- Patent Title: Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
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Application No.: US13994726Application Date: 2011-12-20
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Publication No.: US10795823B2Publication Date: 2020-10-06
- Inventor: Raj K Ramanujan , Glenn J Hinton , David J Zimmerman
- Applicant: Raj K Ramanujan , Glenn J Hinton , David J Zimmerman
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- International Application: PCT/US2011/066302 WO 20111220
- International Announcement: WO2013/095404 WO 20130627
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0891 ; G06F12/0895 ; G06F1/3234 ; G06F1/3225 ; G06F12/0868 ; G06F12/0873 ; G06F12/0804 ; G06F12/0864
Abstract:
A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.
Public/Granted literature
- US20140304475A1 DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY HIERARCHY Public/Granted day:2014-10-09
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