Invention Grant
- Patent Title: Divided integrity verification using memory segment protection
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Application No.: US15701082Application Date: 2017-09-11
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Publication No.: US10796003B2Publication Date: 2020-10-06
- Inventor: Naoko Yamada , Jun Kanai , Shinya Takumi , Hiroshi Isozaki
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@67c7b808
- Main IPC: G06F21/57
- IPC: G06F21/57 ; G06F21/51 ; G06F21/64 ; G06F12/02 ; G06F21/55 ; G06F21/52 ; G06F12/14

Abstract:
According to one embodiment, an information processing apparatus includes a first memory, a signal generation unit, an integrity check unit, and an access-right update unit. Firmware is stored in the first memory. The signal generation unit is configured to generate a signal when there is access violating access right, to the first memory. The integrity check unit is configured to perform, when the access violating access right is a verification request with respect to a predetermined verification target region, integrity check with respect to the verification target region in response to the signal. The access-right update unit is configured to update access right corresponding to the verification target region, to which the integrity check has been performed.
Public/Granted literature
- US20180137285A1 INFORMATION PROCESSING APPARATUS AND COMPUTER PROGRAM PRODUCT Public/Granted day:2018-05-17
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