Systems and methods for re-ordering test patterns for circuit design or testing. A method includes receiving a set of scan chains and associated test patterns, and computing a penalty score for each test pattern in the set of test patterns. The method includes selecting a first pattern of the set of test patterns that has a lowest computed penalty score in the set of test patterns, and removing the first pattern from the set of test patterns and adding the first pattern to a set of ordered patterns. The method includes, for each remaining test pattern, computing an accumulated penalty score for each remaining pattern, selecting a next pattern of the set of test patterns that has a lowest accumulated penalty score in the set of test patterns, removing the next pattern from the set of test patterns, and adding the next pattern to the set of ordered patterns.