Invention Grant
- Patent Title: Machine learning-based parasitic extraction automation for circuit design and verification
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Application No.: US16549929Application Date: 2019-08-23
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Publication No.: US10796046B2Publication Date: 2020-10-06
- Inventor: Vasileios Kourkoulos , Rengjing Zhang , Joshua Adkins
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Mentor Graphics Corporation
- Main IPC: G06F30/00
- IPC: G06F30/00 ; G06F30/327 ; G06N20/00

Abstract:
This application discloses a computing system implementing a parasitic extraction tool to generate parasitic netlists from tests cases including test layout models of integrated circuit structures. The test cases include reference netlists corresponding to intended parasitic netlists for the test layout models. The computing system can determine values for scaling coefficients that, when utilized by the parasitic extraction tool to generate the parasitic netlists, allow differences between the parasitic netlists and the reference netlists to fall below threshold levels. The determination of the scaling coefficients is performed by iteratively adjusting the values of the scaling coefficients based on differences between the reference netlists and the parasitic netlists generated with the scaling coefficients having the adjusted values. The computing system can utilize the adjusted scaling coefficients to generate parasitic netlists having differences with the reference netlists that fall below threshold levels of the test cases.
Public/Granted literature
- US20200233931A1 MACHINE LEARNING-BASED PARASITIC EXTRACTION AUTOMATION FOR CIRCUIT DESIGN AND VERIFICATION Public/Granted day:2020-07-23
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