Invention Grant
- Patent Title: Functional safety synthesis
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Application No.: US16254324Application Date: 2019-01-22
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Publication No.: US10796047B2Publication Date: 2020-10-06
- Inventor: Sanjay Pillay , Arum Kumar Gogineni , Srikanth Rengarajan
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Mentor Graphics Corporation
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/33 ; G06F30/3323

Abstract:
This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the safety circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, wherein a logical equivalency checking tool can be utilized to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, wherein at least one verification tool can be utilized in a verification environment to simulate the modified circuit design.
Public/Granted literature
- US20190228125A1 FUNCTIONAL SAFETY SYNTHESIS Public/Granted day:2019-07-25
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