Invention Grant
- Patent Title: Waveform propagation timing modeling for circuit design
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Application No.: US16228481Application Date: 2018-12-20
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Publication No.: US10796049B1Publication Date: 2020-10-06
- Inventor: Kwangsoo Han , Zhuo Li , Charles Jay Alpert
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F30/3312 ; G06F30/337 ; G06F111/10 ; G06F119/12 ; G06F30/30

Abstract:
Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.
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