Methods, systems, and devices related to memory, including read or write performance of a phase change memory, are described. A plurality of memory cells of a memory array may be read. A total number of read errors resulting from the read operation of the plurality of memory cells may be determined, and reference read currents may be adjusted if the total number of read errors exceeds an error threshold. In some examples, adjusting reference read currents includes reading a reference memory cell, determining a current shift for the reference memory cell, and adjusting read currents for other memory cells of the memory array by a current delta based at least in part on the current shift.