Invention Grant
- Patent Title: Integrated fan-out package and method of fabricating an integrated fan-out package
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Application No.: US16594089Application Date: 2019-10-07
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Publication No.: US10797023B2Publication Date: 2020-10-06
- Inventor: Hung-Jui Kuo , Yu-Hsiang Hu , Sih-Hao Liao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L23/498 ; H01L23/31 ; H01L23/00 ; H01L21/56 ; H01L23/538

Abstract:
A method of fabricating an INFO package may include at least the following steps. A first buffer pattern and a second buffer pattern are formed on a substrate. A first chip is attached on the substrate through the first buffer pattern. A second chip is attached on the substrate through the second buffer pattern. A squeezing force is provided between an exterior surface of the substrate and a top surface of the first chip and between an exterior surface of the substrate and a top surface of the second chip. The squeezed first buffer pattern and the squeezed second buffer pattern are cured. A molding compound is formed surrounding the first chip, the second chip, the squeezed first buffer pattern and the squeezed second buffer pattern. A redistribution circuit structure layer is formed electrically connected to the first chip and the second chip on the molding compound.
Public/Granted literature
- US20200035648A1 INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING AN INTEGRATED FAN-OUT PACKAGE Public/Granted day:2020-01-30
Information query
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