Invention Grant
- Patent Title: Integrated circuit device having a plurality of stacked dies
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Application No.: US16511796Application Date: 2019-07-15
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Publication No.: US10797037B1Publication Date: 2020-10-06
- Inventor: Qi Lin
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G11C5/06
- IPC: G11C5/06 ; H01L25/18 ; H01L25/00 ; G11C7/10 ; H01L23/48 ; G11C8/12

Abstract:
An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device comprises a first die of the plurality of stacked dies having an input/output element configured to receive an input signal, the first die comprising a signal driver circuit configured to provide the input signal to each die of the plurality of stacked dies and a chip select circuit for generating a plurality of chip select signals for the plurality of stacked dies; and a second die of the plurality of stacked dies coupled to the first die, the second die having a function block configured to the receive the input signal; wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals that corresponds to the second die. A method of implementing an integrated circuit device having a plurality of stacked dies is also described.
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