Invention Grant
- Patent Title: Gate isolation in non-planar transistors
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Application No.: US15777260Application Date: 2015-12-26
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Publication No.: US10797047B2Publication Date: 2020-10-06
- Inventor: Leonard P. Guler , Gopinath Bhimarasetti , Vyom Sharma , Walid M. Hafez , Christopher P. Auth
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/US2015/000377 WO 20151226
- International Announcement: WO2017/111819 WO 20170629
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/66 ; H01L29/78 ; H01L21/8234 ; H01L29/06 ; H01L29/51

Abstract:
An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.
Public/Granted literature
- US20180331098A1 GATE ISOLATION IN NON-PLANAR TRANSISTORS Public/Granted day:2018-11-15
Information query
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