Invention Grant
- Patent Title: Memory cell comprising first and second transistors and methods of operating
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Application No.: US16219359Application Date: 2018-12-13
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Publication No.: US10797055B2Publication Date: 2020-10-06
- Inventor: Yuniarto Widjaja , Jin-Woo Han , Benjamin S. Louie
- Applicant: Zeno Semiconductor, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Zeno Semiconductor, Inc.
- Current Assignee: Zeno Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agent Alan W. Cannon
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/78 ; H01L29/70 ; G11C11/404 ; H01L29/73 ; G11C16/04 ; G11C16/10 ; H01L27/11524 ; H01L27/102 ; H01L29/08 ; H01L29/10 ; H01L29/36 ; G11C16/26 ; G11C16/34 ; H01L29/732
Abstract:
Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.
Public/Granted literature
- US20190131305A1 Memory Cell Comprising First and Second Transistors and Methods of Operating Public/Granted day:2019-05-02
Information query
IPC分类:
