A semiconductor memory device includes a semiconductor substrate, a pillar disposed above the semiconductor substrate and extending in a first direction crossing a principal surface of the semiconductor substrate, a plurality of first memory cells arranged on a first side surface of the pillar along the first direction, and a plurality of second memory cells arranged on a second side surface of the pillar along the first direction. The memory device further includes a plurality of first control gate layers respectively connected to the first memory cells, a plurality of second control gate layers respectively connected to the second memory cells, and a stacked film disposed between one of the first control gate layers and one of the second control gate layers, the stacked film including a first insulating layer, a second insulating layer, and an electron capture layer disposed between the first insulating layer and the second insulating layer.