Invention Grant
- Patent Title: Asymmetric source/drain regions of transistors
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Application No.: US16209495Application Date: 2018-12-04
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Publication No.: US10797135B2Publication Date: 2020-10-06
- Inventor: Si-Woo Lee , Yunfei Gao , Srinivas Pulugurtha
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L29/08 ; H01L27/108 ; H01L21/8234 ; H01L27/088

Abstract:
An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.
Public/Granted literature
- US20200176564A1 ASYMMETRIC SOURCE/DRAIN REGIONS OF TRANSISTORS Public/Granted day:2020-06-04
Information query
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