Invention Grant
- Patent Title: Method of forming the gate electrode of field effect transistor
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Application No.: US16724752Application Date: 2019-12-23
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Publication No.: US10797156B2Publication Date: 2020-10-06
- Inventor: Neng-Kuo Chen , Clement Hsingjen Wann , Yi-An Lin , Chun-Wei Chang , Sey-Ping Sun
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/3105 ; H01L29/78 ; H01L21/8238 ; H01L21/28 ; H01L21/321 ; H01L21/3213 ; H01L29/165

Abstract:
A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
Public/Granted literature
- US20200127118A1 METHOD OF FORMING THE GATE ELECTRODE OF FIELD EFFECT TRANSISTOR Public/Granted day:2020-04-23
Information query
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