Invention Grant
- Patent Title: Dual magnetic tunnel junction (DMTJ) stack design
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Application No.: US16133964Application Date: 2018-09-18
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Publication No.: US10797225B2Publication Date: 2020-10-06
- Inventor: Vignesh Sundar , Yu-Jen Wang , Luc Thomas , Guenole Jan , Sahil Patel , Ru-Ying Tong
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L43/02
- IPC: H01L43/02 ; H01F10/32 ; G11C11/16 ; H01L43/12 ; H01F41/34 ; H01L43/10
Abstract:
A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2/capping layer configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL1 and PL2, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RACAP is formed on PL2 to provide higher PL2 stability. The condition RA1
Public/Granted literature
- US20200091408A1 Dual Magnetic Tunnel Junction (DMTJ) Stack Design Public/Granted day:2020-03-19
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