Invention Grant
- Patent Title: Hierarchical buffering scheme to normalize non-volatile media raw bit error rate transients
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Application No.: US15926973Application Date: 2018-03-20
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Publication No.: US10802907B2Publication Date: 2020-10-13
- Inventor: Samuel E. Bradshaw
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/08 ; G06F3/06 ; G11C13/00 ; G06F11/07

Abstract:
A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.
Public/Granted literature
- US20190294493A1 HIERARCHICAL BUFFERING SCHEME TO NORMALIZE NON-VOLATILE MEDIA RAW BIT ERROR RATE TRANSIENTS Public/Granted day:2019-09-26
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