Invention Grant
- Patent Title: Master slave level shift latch for word line decoder memory architecture
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Application No.: US16294920Application Date: 2019-03-07
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Publication No.: US10803949B2Publication Date: 2020-10-13
- Inventor: Neal Berger , Susmita Karmakar , Benjamin Louie
- Applicant: SPIN MEMORY, Inc.
- Applicant Address: US CA Fremont
- Assignee: Spin Memory, Inc.
- Current Assignee: Spin Memory, Inc.
- Current Assignee Address: US CA Fremont
- Main IPC: G11C8/10
- IPC: G11C8/10 ; G11C16/08 ; H01L27/11 ; H01L43/08 ; G11C11/16
Abstract:
A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.
Public/Granted literature
- US20200286561A1 Master Slave Level Shift Latch for Word Line Decoder Memory Architecture Public/Granted day:2020-09-10
Information query
