Invention Grant
- Patent Title: Systems and methods for producing flat surfaces in interconnect structures
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Application No.: US15834354Application Date: 2017-12-07
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Publication No.: US10804151B2Publication Date: 2020-10-13
- Inventor: Cyprian Emeka Uzoh , Vage Oganesian , Ilyas Mohammed
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lee & Hayes, P.C.
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L21/321 ; H01L23/48 ; H01L23/532

Abstract:
In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.
Public/Granted literature
- US20180102286A1 SYSTEMS AND METHODS FOR PRODUCING FLAT SURFACES IN INTERCONNECT STRUCTURES Public/Granted day:2018-04-12
Information query
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