- Patent Title: Porous silicon relaxation medium for dislocation free CMOS devices
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Application No.: US16598517Application Date: 2019-10-10
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Publication No.: US10804166B2Publication Date: 2020-10-13
- Inventor: Kangguo Cheng , Ramachandra Divakaruni , Jeehwan Kim , Juntao Li , Devendra K. Sadana
- Applicant: ELPIS TECHNOLOGIES INC.
- Applicant Address: CA
- Assignee: ELPIS TECHNOLOGIES INC.
- Current Assignee: ELPIS TECHNOLOGIES INC.
- Current Assignee Address: CA
- Agency: Tutunjian & Bitetto, P.C.
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L27/12 ; H01L27/092 ; H01L21/8238 ; H01L29/161 ; H01L21/02 ; H01L21/306 ; H01L29/167 ; H01L21/326 ; H01L21/265 ; H01L21/762 ; H01L29/06 ; H01L29/78

Abstract:
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
Public/Granted literature
- US20200043811A1 POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES Public/Granted day:2020-02-06
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