A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.