Invention Grant
- Patent Title: Method of manufacturing semiconductor device
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Application No.: US16368512Application Date: 2019-03-28
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Publication No.: US10818682B2Publication Date: 2020-10-27
- Inventor: Shigeki Katou
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4c76ad5e
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/11568 ; H01L27/11565 ; H01L27/11573 ; H01L29/78 ; H01L21/768 ; H01L21/321 ; H01L21/311 ; H01L29/66 ; H01L21/28 ; H01L21/762

Abstract:
To provide, in an increased production yield, a reliability-improved semiconductor product having both a planar type transistor and a fin type transistor. A semiconductor device having both a planar type transistor and a fin type transistor is manufactured by decreasing the thickness of a hard mask for the formation of element isolation in the planar type transistor region prior to formation of element isolation in the fin type transistor region.
Public/Granted literature
- US20190312048A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2019-10-10
Information query
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