A vertical memory device includes a gate structure including a first gate electrode on a peripheral circuit region of a substrate, the substrate containing a cell region and the peripheral circuit region, a plurality of second gate electrodes sequentially stacked on the cell region of the substrate, the plurality of second gate electrodes spaced apart from each other in a vertical direction to an upper surface of the substrate, a channel extending in the vertical direction on the cell region of the substrate and extending through at least one of the second gate electrodes, and a first insulating interlayer covering the gate structure on the peripheral circuit region of the substrate, a cross-section in one direction of an upper surface of a portion of the first insulating interlayer overlapping the gate structure in the vertical direction having a shape of a portion of a polygon.