An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.