Selectively preventing pre-coherence point reads in a cache hierarchy to reduce barrier overhead
Abstract:
A data processing system includes a processor core having a shared store-through upper level cache and a store-in lower level cache. The processor core executes a plurality of simultaneous hardware threads of execution including at least a first thread and a second thread, and the shared store-through upper level cache stores a first cache line accessible to both the first thread and the second thread. The processor core executes in the first thread a store instruction that generates a store request specifying a target address of a storage location corresponding to the first cache line. Based on the target address hitting in the shared store-through upper level cache, the first cache line is temporarily marked, in the shared store-through upper level cache, as private to the first thread, such that any memory access request by the second thread targeting the storage location will miss in the shared store-through upper level cache.
Information query
Patent Agency Ranking
0/0