Invention Grant
- Patent Title: Selectively preventing pre-coherence point reads in a cache hierarchy to reduce barrier overhead
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Application No.: US16209604Application Date: 2018-12-04
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Publication No.: US10824567B2Publication Date: 2020-11-03
- Inventor: Derek E. Williams , Hugh Shen , Guy L. Guthrie , William J. Starke
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent David Quinn; Brian F. Russell
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/084 ; G06F9/52 ; G06F9/30 ; G06F12/12

Abstract:
A data processing system includes a processor core having a shared store-through upper level cache and a store-in lower level cache. The processor core executes a plurality of simultaneous hardware threads of execution including at least a first thread and a second thread, and the shared store-through upper level cache stores a first cache line accessible to both the first thread and the second thread. The processor core executes in the first thread a store instruction that generates a store request specifying a target address of a storage location corresponding to the first cache line. Based on the target address hitting in the shared store-through upper level cache, the first cache line is temporarily marked, in the shared store-through upper level cache, as private to the first thread, such that any memory access request by the second thread targeting the storage location will miss in the shared store-through upper level cache.
Public/Granted literature
- US20200174931A1 SELECTIVELY PREVENTING PRE-COHERENCE POINT READS IN A CACHE HIERARCHY TO REDUCE BARRIER OVERHEAD Public/Granted day:2020-06-04
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