Invention Grant
- Patent Title: Memory system
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Application No.: US16562730Application Date: 2019-09-06
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Publication No.: US10824570B2Publication Date: 2020-11-03
- Inventor: Satoshi Kaburaki , Tetsuhiko Azuma
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4886465a
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/10 ; G06F3/06 ; G06F12/02

Abstract:
A first memory stores a translation table indicating a first correspondence between a logical address and a physical address at first timing. A second memory stores a difference table that is configured to record, in each of entries, a correspondence between a logical address range and a physical address range, the correspondence representing a difference between the first correspondence and a second correspondence. The second correspondence is between the logical address and the physical address at second timing. In non-volatilizing data in a first logical address range to a first physical address range, in a case where the entries includes a first entry containing a correspondence between a second logical address range and a second physical address range, the controller updates the first entry. The first logical address range follows the second logical address range, and the first physical address range follows the second physical address range.
Public/Granted literature
- US20200226069A1 MEMORY SYSTEM Public/Granted day:2020-07-16
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