Invention Grant
- Patent Title: Low-power adder circuit
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Application No.: US16159450Application Date: 2018-10-12
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Publication No.: US10824692B2Publication Date: 2020-11-03
- Inventor: Anand Suresh Kane , Ravi Narayanaswami
- Applicant: Google LLC
- Applicant Address: US CA Mountain View
- Assignee: Google LLC
- Current Assignee: Google LLC
- Current Assignee Address: US CA Mountain View
- Agency: Fish & Richardson P.C.
- Main IPC: G06F7/485
- IPC: G06F7/485 ; G06F17/10 ; G06F7/50 ; G06N3/063

Abstract:
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.
Public/Granted literature
- US20200117696A1 LOW-POWER ADDER CIRCUIT Public/Granted day:2020-04-16
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