Device for implementing artificial neural network with flexible buffer pool structure
Abstract:
The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer pool, a data reading scheduling unit and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.
Information query
Patent Agency Ranking
0/0