A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.