Invention Grant
- Patent Title: Low latency memory erase suspend operation
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Application No.: US14455749Application Date: 2014-08-08
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Publication No.: US10825529B2Publication Date: 2020-11-03
- Inventor: Wen-Ming Hsu , Nai-Ping Kuo , Chun-Hsiung Hung
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/16

Abstract:
A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.
Public/Granted literature
- US20160042796A1 LOW LATENCY MEMORY ERASE SUSPEND OPERATION Public/Granted day:2016-02-11
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