Invention Grant
- Patent Title: 3D CTF integration using hybrid charge trap layer of sin and self aligned SiGe nanodot
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Application No.: US15493690Application Date: 2017-04-21
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Publication No.: US10825681B2Publication Date: 2020-11-03
- Inventor: Thomas Jongwan Kwon , Sungwon Jun
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/02 ; H01L29/04 ; H01L21/28 ; H01L29/423 ; H01L29/788 ; H01L27/11524 ; H01L27/11556 ; H01L29/16

Abstract:
Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).
Public/Granted literature
- US20180047743A1 3D CTF INTEGRATION USING HYBRID CHARGE TRAP LAYER OF SIN AND SELF ALIGNED SIGE NANODOT Public/Granted day:2018-02-15
Information query
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