Invention Grant
- Patent Title: Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
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Application No.: US16410842Application Date: 2019-05-13
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Publication No.: US10825693B2Publication Date: 2020-11-03
- Inventor: Jing-Cheng Lin , Shih Ting Lin , Chen-Hua Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L21/56 ; H01L23/31

Abstract:
An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.
Public/Granted literature
- US20190267255A1 CARRIER WARPAGE CONTROL FOR THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) STACKING Public/Granted day:2019-08-29
Information query
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