Invention Grant
- Patent Title: Spacers for nanowire-based integrated circuit device and method of fabricating same
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Application No.: US16679934Application Date: 2019-11-11
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Publication No.: US10825915B2Publication Date: 2020-11-03
- Inventor: Tung Ying Lee , Shao-Ming Yu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L29/786 ; H01L29/165 ; H01L27/092 ; H01L21/8238 ; H01L29/423 ; H01L29/40 ; H01L29/775 ; H01L29/06 ; B82Y10/00

Abstract:
Gate-all-around (GAA) devices and methods for fabricating such are disclosed herein. An exemplary GAA device includes a first semiconductor layer disposed over a substrate. A gate structure is disposed over and wraps a portion of the first semiconductor layer, such that the gate structure separates a source region of the first semiconductor layer and a drain region of the first semiconductor layer. A channel region of the first semiconductor layer is defined between the source region and the drain region. A dielectric layer is disposed adjacent to the first semiconductor layer, where the dielectric layer extends along an entirety of the source region of the first semiconductor layer and an entirety of the drain region of the first semiconductor layer. A second semiconductor layer disposed over the source region of the first semiconductor layer, the drain region of the first semiconductor layer, and the dielectric layer.
Public/Granted literature
- US20200075743A1 Spacers for Nanowire-Based Integrated Circuit Device and Method of Fabricating Same Public/Granted day:2020-03-05
Information query
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