Embodiments of the present disclosure relate to a method and device for cache management. The method includes: receiving an I/O request associated with a processor kernel; in response to first data that the I/O request is targeted for being missed in a cache, determining whether a first target address of the first data is recorded in one of a plurality of cache history lists; in response to the first target address not being recorded in the plurality of cache history lists, storing, in a first node of a first free cache history list, the first target address and an initial access count of the first target address, the first free cache history list being determined in association with the processor kernel in advance; and adding the first node to a first cache history list associated with the I/O request of the plurality of cache history lists.