Invention Grant
- Patent Title: System and method to improve input output command latency by dynamic size logical to physical caching
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Application No.: US16157076Application Date: 2018-10-10
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Publication No.: US10831656B2Publication Date: 2020-11-10
- Inventor: Jameer Babasaheb Mulani , Anindya Rai , Devanathan Balasundaram
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan, LLP
- Agent Steven H. Versteeg
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/28 ; G06F12/0802 ; G06F13/16
Abstract:
A method and apparatus are provided to divide a logical to physical table into multiple parts, one part in a first fast memory and a second part in a second non-volatile memory, wherein an algorithm may be used in the division.
Public/Granted literature
- US20200117598A1 SYSTEM AND METHOD TO IMPROVE INPUT OUTPUT COMMAND LATENCY BY DYNAMIC SIZE LOGICAL TO PHYSICAL CACHING Public/Granted day:2020-04-16
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