Invention Grant
- Patent Title: Multi-tier cache placement mechanism
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Application No.: US15819460Application Date: 2017-11-21
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Publication No.: US10831678B2Publication Date: 2020-11-10
- Inventor: Jiajun Wang , Prakash S. Ramrakhyani , Wei Wang , Wendy Arnott Elsasser
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Leveque IP Law, P.C.
- Main IPC: G06F12/126
- IPC: G06F12/126 ; G06F12/0862 ; G06F12/0811 ; G06F12/0888

Abstract:
Storage of data in a cache system is controlled by a cache monitor. A cache line is filled in response to a memory instruction from a cache client. The cache monitor includes a predictor table and update logic. An entry in the predictor table comprises an instruction identifier that associates the entry with a memory instruction and, for each cache in the system, a reuse counter. The update logic is configured to update a reuse counter table dependent upon cache behavior in response to memory instructions. Storage of data a first data address in cache in response to a memory instruction having a first instruction identifier, is dependent upon reuse counter values in an entry of the predictor table associated with first instruction identifier. Reuse counters are updated dependent upon cache behavior. A Bloom filter or other data structure may be used to associate data addresses with a memory instruction.
Public/Granted literature
- US20190155750A1 MULTI-TIER CACHE PLACEMENT MECHANISM Public/Granted day:2019-05-23
Information query
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