Techniques for logic partition identifiers for an integrated circuit (IC) design are described herein. An aspect includes receiving a logic domain representation of an IC design comprising a plurality of logic partitions each comprising a respective plurality of IC elements. Another aspect includes generating a physical domain representation of the IC design based on the logic domain representation comprising a plurality of logic clusters each corresponding to a respective logic partition, wherein each of the plurality of logic clusters comprises a respective plurality of IC elements. Another aspect includes assigning a logic partition identifier to each IC element in the physical domain representation, wherein the logic partition identifier of an IC element corresponds to a logic partition. Another aspect includes determining timing information for a logic partition based on the logic partition identifiers of the plurality of IC elements of a logic cluster associated with the logic partition.